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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CNTV_TVAL, Counter-timer Virtual Timer TimerValue</h1><p>The CNTV_TVAL characteristics are:</p><h2>Purpose</h2>
        <p>Holds the timer value for the virtual timer.</p>
      <h2>Configuration</h2><p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether CNTV_TVAL is implemented in the Core power domain or in the Debug power domain.
    </p>
        <p>For more information, see <span class="xref">'Power and reset domains for the system level implementation of the Generic Timer'</span>.</p>
      <h2>Attributes</h2>
        <p>CNTV_TVAL is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-31_0">TimerValue</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">TimerValue, bits [31:0]</h4><div class="field"><p>The TimerValue view of the virtual timer.</p>
<p>On a read of this register:</p>
<ul>
<li>If <a href="ext-cntv_ctl.html">CNTV_CTL</a>.ENABLE is 0, the value returned is <span class="arm-defined-word">UNKNOWN</span>.
</li><li>If <a href="ext-cntv_ctl.html">CNTV_CTL</a>.ENABLE is 1, the value returned is (CompareValue - <a href="ext-cntvct.html">CNTVCT</a>).
</li></ul>
<p>On a write of this register, CompareValue is set to (<a href="ext-cntvct.html">CNTVCT</a> + TimerValue), where TimerValue is treated as a signed 32-bit integer.</p>
<p>When <a href="ext-cntv_ctl.html">CNTV_CTL</a>.ENABLE is 1, the timer condition is met when (<a href="ext-cntvct.html">CNTVCT</a> - CompareValue) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:</p>
<ul>
<li><a href="ext-cntv_ctl.html">CNTV_CTL</a>.ISTATUS is set to 1.
</li><li>If <a href="ext-cntv_ctl.html">CNTV_CTL</a>.IMASK is 0, an interrupt is generated.
</li></ul>
<p>When <a href="ext-cntv_ctl.html">CNTV_CTL</a>.ENABLE is 0, the timer condition is not met, but <a href="ext-cntvct.html">CNTVCT</a> continues to count, so the TimerValue view appears to continue to count down.</p><p>The reset behavior of this field is:</p><ul><li>On a Timer reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing CNTV_TVAL</h2>
        <p>CNTV_TVAL can be implemented in any implemented CNTBaseN frame that has virtual timer capability, and in the corresponding CNTEL0BaseN frame.</p>

      
        <p><span class="xref">'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames'</span> describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:</p>

      
        <ul>
<li>Whether the CNTBaseN frame has virtual timer capability.
</li><li>Whether the corresponding CNTEL0BaseN frame is implemented.
</li><li>For an implementation that recognizes two Security states, whether the CNTBaseN frame, and any corresponding CNTEL0BaseN frame, is accessible by Non-secure accesses.
</li></ul>

      
        <p>For an implemented CNTBaseN frame that has virtual timer capability:</p>

      
        <ul>
<li>CNTV_TVAL is accessible in that frame if the value of <a href="ext-cntacrn.html">CNTACR&lt;n&gt;</a>.RWVT is 1.
</li><li>Otherwise, the CNTV_TVAL address in that frame is RAZ/WI.
</li></ul>

      
        <p>For an implemented CNTEL0BaseN frame:</p>

      
        <ul>
<li>CNTV_TVAL is accessible in that frame if both:<ul>
<li>CNTV_TVAL is accessible in the corresponding CNTBaseN frame.
</li><li>The value of <a href="ext-cntel0acr.html">CNTEL0ACR</a>.EL0VTEN is 1.
</li></ul>

</li><li>Otherwise, the CNTV_TVAL address in that frame is RAZ/WI.
</li></ul>
      <h4>CNTV_TVAL can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>Timer</td><td>CNTBaseN</td><td><span class="hexnumber">0x038</span></td><td>CNTV_TVAL</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>Timer</td><td>CNTEL0BaseN</td><td><span class="hexnumber">0x038</span></td><td>CNTV_TVAL</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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